Field of the Invention
The invention relates to a method for improving a spurious free dynamic range (SFDR) and a signal-to-noise-and-distortion ratio (SNDR) of a capacitor-resistor combined successive approximation register (SAR) analog-to-digital converter (ADC) by capacitor re-configuration.
Description of the Related Art
Conventional methods for capacitor mismatch calibration of an ADC generally suffer from complicate algorithms, large chip occupation area, and high power consumption. A capacitor-resistor combined architecture is known, as shown in FIG. 1. A typical 14-bit capacitor-resistor architecture SAR ADC includes a 6-bit main capacitive DAC and an 8-bit sub-resistive DAC, and the 6-bit main capacitive DAC includes 64 unit capacitors. Such capacitor-resistor combined architecture has excellent static linearity and no floating nodes. However, the calibration circuit is relatively complex, the operation of such ADC is sensitive to working environment, and the SFDR and SNDR leave much to be desired.